Relaxed silicon-germanium (SiGe) virtual substrates with low defect densities are an advantageous platform for integration of high-speed heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) onto silicon substrates. Enhanced performance of n-type MOSFETs (NMOS transistors) has been demonstrated with heterojunction MOSFETs built on substrates having strained silicon (Si) and relaxed SiGe layers. Tensile strained silicon greatly enhances electron mobilities. NMOS devices with strained silicon surface channels, therefore, have improved performance with higher switching speeds. Hole mobilities are enhanced in tensile strained silicon as well, but to a lesser extent for strain levels less than approximately 1.5%. Accordingly, equivalent enhancement of p-type MOS (PMOS) device performance in such surface-channel devices presents a challenge.
In bulk Si, the ratio of electron mobility to hole mobility is approximately 2. Therefore, even with symmetric mobility enhancements over bulk Si, hole mobility in strained Si PMOS devices is still considerably lower than electron mobility in strained Si NMOS devices. Low hole mobilities require increased PMOS gate widths to compensate for the reduced drive currents of PMOS devices. The resulting increased chip area taken up by PMOS devices consumes valuable device space, while the mismatch in NMOS and PMOS areas reduces logic speed through capacitive delays. Symmetric current drive from NMOS and PMOS, theoretically attainable through symmetric, i.e., equal, electron and hole mobilities would eliminate this source of capacitive delay, thereby increasing overall circuit speed. Device heterostructures with symmetric electron and hole mobilities, however, are not yet available. These factors encourage circuit designers to avoid PMOS in logic circuits whenever possible.
High mobility layers offer improvements for PMOS design. A promising route for integration of high hole mobility devices with high electron mobility strained Si NMOS devices is through the use of buried, compressively strained Si1−yGey layers and surface strained Si layers, grown on a relaxed Si1−xGex virtual substrate (x<y), hereafter referred to as “dual channel heterostructures.” Dual channel heterostructures allow simultaneous integration of hole and electron channel devices within the same layer sequence. While the high mobility of compressively strained Ge-rich hole channels in modulation doped layers has been well documented, devices based upon these layers are typically Schottky-gated and depletion mode, both of which are incompatible with mainstream Si CMOS schemes.
Theoretical and experimental results, however, indicate that dual channel structures provide worthwhile PMOS device performance without the need for modulation doping, while retaining a high quality silicon/silicon dioxide (Si/SiO2) interface. For example, the combination of a buried compressively strained Si0.17Ge0.83 channel and a surface tensile strained Si channel provides room temperature hole mobilities of over 700 cm2V-s (see, e.g., G. Hoeck et al., Appl. Phys. Lett., 76:3920, 2000, incorporated herein by reference). This concept has also been extended to pure Ge channel MOSFETs, in which even higher hole mobility enhancements have been attained (see, e.g., M. L. Lee, et al., Applied Physics Letters 79:3344, 2001, incorporated herein by reference). Furthermore, simulations reveal that electron mobility in the strained Si surface channel is not degraded by the presence of the buried SiGe layer, making this structure suitable for both electron and hole channel devices (see, e.g., M. A. Armstrong, Ph.D. Thesis, MIT, 1999).